05-04-2017, 02:22 AM
SYLLABUS:-
UNIT I
Introduction to VHDL, design units, data objects, signal drivers, inertial and transport delays, delta delay, VHDL data types, concurrent and sequential statements. Subprograms – Functions, Procedures, attributes, generio, generate, package, IEEE standard logic library, file I/O, test bench, component declaration, instantiation, configuration.
UNIT II
Combinational logic circuit design and VHDL implementation of following circuits –first adder, Subtractor, decoder, encoder, multiplexer, ALU, barrel shifter, 4X4 key board encoder, multiplier, divider, Hamming code encoder and correction circuits.
UNIT III
Synchronous sequential circuits design – finite state machines, Mealy and Moore, state assignments, design and VHDL implementation of FSMs, Linear feedback shift register (Pseudorandom and CRC).
UNIT IV
Asynchronous sequential circuit design – primitive flow table, concept of race, critical race and hazards, design issues like metastability, synchronizers, clock skew and timing considerations Introduction to place & route process, Introduction to ROM, PLA, PAL, Architecture of CPLD (Xilinx/Altera).
UNIT I
Introduction to VHDL, design units, data objects, signal drivers, inertial and transport delays, delta delay, VHDL data types, concurrent and sequential statements. Subprograms – Functions, Procedures, attributes, generio, generate, package, IEEE standard logic library, file I/O, test bench, component declaration, instantiation, configuration.
UNIT II
Combinational logic circuit design and VHDL implementation of following circuits –first adder, Subtractor, decoder, encoder, multiplexer, ALU, barrel shifter, 4X4 key board encoder, multiplier, divider, Hamming code encoder and correction circuits.
UNIT III
Synchronous sequential circuits design – finite state machines, Mealy and Moore, state assignments, design and VHDL implementation of FSMs, Linear feedback shift register (Pseudorandom and CRC).
UNIT IV
Asynchronous sequential circuit design – primitive flow table, concept of race, critical race and hazards, design issues like metastability, synchronizers, clock skew and timing considerations Introduction to place & route process, Introduction to ROM, PLA, PAL, Architecture of CPLD (Xilinx/Altera).
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