![]() |
DE Digital electronics NOTES, previous year papers, syllabus free downlaod MDU BTECH - Printable Version +- studentsuvidha (https://studentsuvidha.com/forum) +-- Forum: Engineering zone (https://studentsuvidha.com/forum/Forum-Engineering-zone) +--- Forum: Mdu B.Tech papers and Notes- free download (https://studentsuvidha.com/forum/Forum-Mdu-B-Tech-papers-and-Notes-free-download) +---- Forum: Information technology MDU btech papers and Notes -free downloads (https://studentsuvidha.com/forum/Forum-Information-technology-MDU-btech-papers-and-Notes-free-downloads) +----- Forum: 3rd semester IT mdu btech papers and Notes (https://studentsuvidha.com/forum/Forum-3rd-semester-IT-mdu-btech-papers-and-Notes) +----- Thread: DE Digital electronics NOTES, previous year papers, syllabus free downlaod MDU BTECH (/Thread-DE-Digital-electronics-NOTES-previous-year-papers-syllabus-free-downlaod-MDU-BTECH) |
DE Digital electronics NOTES, previous year papers, syllabus free downlaod MDU BTECH - admin - 02-26-2015 DOWNLOAD ALL PREVIOUS YEAR PAPERS HERE of both old and new scheme
SYLLABUS:- SECTION-A Digital system and binary numbers: Signed binary numbers, binary codes, cyclic codes, error detecting and correcting codes, hamming codes. Gate-level minimization: The K-map method up to five variable, don’t care conditions, POS simplification, NAND and NOR implementation, Quine Mc-Clusky method (Tabular method) SECTION-B Combinational Logic: Combinational circuits, analysis procedure, design procedure, binary adder-subtractor, decimal adder, binary multiplier, magnitude comparator, decoders, encoders, multiplexers ,demultiplexers SECTION –C Synchronous Sequential logic: Sequential circuits, storage elements: latches, flip flops, analysis of clocked sequential circuits, state reduction and assignments, design procedure. Registers and counters: Shift registers, ripple counter, synchronous counter, other counters SECTION- D Memory and programmable logic: RAM, ROM, PLA, PAL. Design at the register transfer level: ASMs, design example, design with multiplexers. Asynchronous sequential logic: Analysis procedure, circuit with latches, design procedure, reduction of state and flow table, race Free State assignment, hazards |