05-01-2017, 11:31 PM
QUESTION PAPERS:-
SYLLABUS:-
UNIT I
Evolution of VLSI, MOS transistor theory, MOS structure, enhancement & depletion transistor, threshold voltage, MOS device design equations, MOSFET scaling and small geometry effects, MOSFET capacitances. NMOS inverter, CMOS inverter, DC characteristics, static load MOS inverter, pull up/pull down ratio, static & dynamic power dissipation, CMOS & NMOS process technology – explanation of different stages in fabrication, body effect, latch up in CMOS.
UNIT II
Stick diagram and design rules, lambda based design rules, switching characteristics & inter connection effects: rise time, fall time delays, noise margin. CMOS logic gate design: NAND, NOR, XOR and XNOR gates, Transistor sizing, combinational MOS logic circuits: pass transistor and transmission gate designs, Pseudo NMOS logic.
UNIT III
Sequential MOS logic circuits: SR latch, clocked latch and flip flop circuits, CMOS D latch and edge triggered flip flop, dynamic logic circuits; basic principle, non ideal effects, domino CMOS logic, high performance dynamic CMOS circuits, clocking issues, clock distribution.
UNIT IV
VLSI designing methodology, design flow, design Hierarchy, concept of regularity, modularity & locality, VLSI design style, Design quality, computer aided design technology, adder design and multiplier design examples. Low power design concepts using CMOS Technology. [/b]
SYLLABUS:-
UNIT I
Evolution of VLSI, MOS transistor theory, MOS structure, enhancement & depletion transistor, threshold voltage, MOS device design equations, MOSFET scaling and small geometry effects, MOSFET capacitances. NMOS inverter, CMOS inverter, DC characteristics, static load MOS inverter, pull up/pull down ratio, static & dynamic power dissipation, CMOS & NMOS process technology – explanation of different stages in fabrication, body effect, latch up in CMOS.
UNIT II
Stick diagram and design rules, lambda based design rules, switching characteristics & inter connection effects: rise time, fall time delays, noise margin. CMOS logic gate design: NAND, NOR, XOR and XNOR gates, Transistor sizing, combinational MOS logic circuits: pass transistor and transmission gate designs, Pseudo NMOS logic.
UNIT III
Sequential MOS logic circuits: SR latch, clocked latch and flip flop circuits, CMOS D latch and edge triggered flip flop, dynamic logic circuits; basic principle, non ideal effects, domino CMOS logic, high performance dynamic CMOS circuits, clocking issues, clock distribution.
UNIT IV
VLSI designing methodology, design flow, design Hierarchy, concept of regularity, modularity & locality, VLSI design style, Design quality, computer aided design technology, adder design and multiplier design examples. Low power design concepts using CMOS Technology. [/b]