02-26-2015, 09:00 AM
DOWNLOAD ALL PREVIOUS YEAR PAPERS HERE of both old and new scheme
SYLLABUS:-
SECTION-A
Digital system and binary numbers: Signed binary numbers, binary codes, cyclic codes, error
detecting and correcting codes, hamming codes.
Gate-level minimization: The K-map method up to five variable, don’t care conditions, POS
simplification, NAND and NOR implementation, Quine Mc-Clusky method (Tabular
method)
SECTION-B
Combinational Logic: Combinational circuits, analysis procedure, design procedure, binary
adder-subtractor, decimal adder, binary multiplier, magnitude comparator, decoders,
encoders, multiplexers ,demultiplexers
SECTION –C
Synchronous Sequential logic: Sequential circuits, storage elements: latches, flip flops,
analysis of clocked sequential circuits, state reduction and assignments, design procedure.
Registers and counters: Shift registers, ripple counter, synchronous counter, other counters
SECTION- D
Memory and programmable logic: RAM, ROM, PLA, PAL. Design at the register transfer
level: ASMs, design example, design with multiplexers. Asynchronous sequential logic:
Analysis procedure, circuit with latches, design procedure, reduction of state and flow table,
race Free State assignment, hazards
- DOWNLOAD PAPER OF YEAR 2009
- DOWNLOAD PAPER OF YEAR 2010 please upload
- DOWNLOAD PAPER OF YEAR 2011
- DOWNLOAD PAPER OF YEAR 2012
- DOWNLAOD PAPER OF YEAR 2013
- DOWNLOAD PAPER OF YEAR 2014
- DOWNLOAD PAPER OF YEAR 2015
- DOWNLOAD PAPER OF YEAR 2016
- DOWNLOAD PAPER OF YEAR 2017
SYLLABUS:-
SECTION-A
Digital system and binary numbers: Signed binary numbers, binary codes, cyclic codes, error
detecting and correcting codes, hamming codes.
Gate-level minimization: The K-map method up to five variable, don’t care conditions, POS
simplification, NAND and NOR implementation, Quine Mc-Clusky method (Tabular
method)
SECTION-B
Combinational Logic: Combinational circuits, analysis procedure, design procedure, binary
adder-subtractor, decimal adder, binary multiplier, magnitude comparator, decoders,
encoders, multiplexers ,demultiplexers
SECTION –C
Synchronous Sequential logic: Sequential circuits, storage elements: latches, flip flops,
analysis of clocked sequential circuits, state reduction and assignments, design procedure.
Registers and counters: Shift registers, ripple counter, synchronous counter, other counters
SECTION- D
Memory and programmable logic: RAM, ROM, PLA, PAL. Design at the register transfer
level: ASMs, design example, design with multiplexers. Asynchronous sequential logic:
Analysis procedure, circuit with latches, design procedure, reduction of state and flow table,
race Free State assignment, hazards