QUESTION PAPERS:-
SYLLABUS:-
UNIT- I
Number Systems and Codes:- Decimal, Binary, Octal and Hexadecimal Number systems, Codes- BCD, Gray Code, Excess-3 Code, ASCII, EBCDIC, Conversion between various Codes.
Switching Theory: - Boolean Algebra- Postulates and Theorems, De’ Morgan’s Theorem, Switching Functions- Canonical Forms- Simplification of Switching Functions- Karnaugh Map and Quine Mc-Clusky Methods.
Combinational Logic Circuits:- Review of basic gates- Universal gates, Adder, Subtractor ,Serial Adder, Parallel Adder- Carry Propagate Adder, Carry Look-ahead Adder, Carry Save Adder, Comparators, Parity Generators, Decoder and Encoder, Multiplexer and De-multiplexer, ALU, PLA and PAL.
UNIT- II
Integrated circuits: - TTL and CMOS logic families and their characteristics. Brief introduction to RAM and ROM.
Sequential Logic Circuits: - Latches and Flip Flops- SR, , D, T and MS-JK Flip Flops, Asynchronous Inputs.
Counters and Shift Registers:- Design of Synchronous and Asynchronous Counters:- Binary, BCD, Decade and Up/Down Counters , Shift Registers, Types of Shift Registers, Counters using Shift Registers- Ring Counter and Johnson Counter.
UNIT- III
Synchronous Sequential Circuits:- State Tables State Equations and State Diagrams, State Reduction and State Assignment, Design of Clocked Sequential Circuits using State Equations.
Finite state machine-capabilities and limitations, Mealy and Moore models-minimization of completely specified and incompletely specified sequential machines, Partition techniques and merger chart methodsconcept of minimal cover table.
UNIT- IV
Algorithmic State Machine: Representation of sequential circuits using ASM charts synthesis of output and next state functions, Data path control path partition-based design.
Fault Detection and Location: Fault models for combinational and sequential circuits, Fault detection in combinational circuits; Homing experiments, distinguishing experiments, machine identification and fault detection experiments in sequential circuits.
SYLLABUS:-
UNIT- I
Number Systems and Codes:- Decimal, Binary, Octal and Hexadecimal Number systems, Codes- BCD, Gray Code, Excess-3 Code, ASCII, EBCDIC, Conversion between various Codes.
Switching Theory: - Boolean Algebra- Postulates and Theorems, De’ Morgan’s Theorem, Switching Functions- Canonical Forms- Simplification of Switching Functions- Karnaugh Map and Quine Mc-Clusky Methods.
Combinational Logic Circuits:- Review of basic gates- Universal gates, Adder, Subtractor ,Serial Adder, Parallel Adder- Carry Propagate Adder, Carry Look-ahead Adder, Carry Save Adder, Comparators, Parity Generators, Decoder and Encoder, Multiplexer and De-multiplexer, ALU, PLA and PAL.
UNIT- II
Integrated circuits: - TTL and CMOS logic families and their characteristics. Brief introduction to RAM and ROM.
Sequential Logic Circuits: - Latches and Flip Flops- SR, , D, T and MS-JK Flip Flops, Asynchronous Inputs.
Counters and Shift Registers:- Design of Synchronous and Asynchronous Counters:- Binary, BCD, Decade and Up/Down Counters , Shift Registers, Types of Shift Registers, Counters using Shift Registers- Ring Counter and Johnson Counter.
UNIT- III
Synchronous Sequential Circuits:- State Tables State Equations and State Diagrams, State Reduction and State Assignment, Design of Clocked Sequential Circuits using State Equations.
Finite state machine-capabilities and limitations, Mealy and Moore models-minimization of completely specified and incompletely specified sequential machines, Partition techniques and merger chart methodsconcept of minimal cover table.
UNIT- IV
Algorithmic State Machine: Representation of sequential circuits using ASM charts synthesis of output and next state functions, Data path control path partition-based design.
Fault Detection and Location: Fault models for combinational and sequential circuits, Fault detection in combinational circuits; Homing experiments, distinguishing experiments, machine identification and fault detection experiments in sequential circuits.
This post was last modified: 08-29-2018, 04:39 PM by Dipesh S.